rev.0, 10/08, wk page 1 of 9 MT-075 tutorial differential drivers for high speed adcs overview differential driver basics many high performance adcs are now being de signed with differential inputs. a fully differential adc design offers the advantages of good common-mode re jection, reduction in second-order distortion products, an d simplified dc trim algorithms. although they can be driven single-ended, a fully differential driver usually optimizes overall performance. the reduction in second-order distortion products inherent in differential designs can be illustrated as follows. the distortion products are modeled by expressing the transfer functions of the circuit as a power series. taking a generic expansion of the outputs and assuming matched amplifiers, we get: v out+ = k 1 (v in ) + k 2 (v in ) 2 + k 3 (v in ) 3 + . . . eq. 1 v out? = k 1 (?v in )+ k 2 (?v in ) 2 + k 3 (?v in ) 3 + . . . eq. 2 taking the differential output: v out+ ? v out? = 2k 1 (v in ) + 2k 3 (v in ) 3 + . . . eq. 3 where k 1 , k 2 and k 3 are constants. the quadratic terms gives rise to second-order ha rmonic distortion, the cubic terms gives rise to third-order harmonic distortion, and so on. in a fu lly-differential amplifie r, the odd-order terms retain their polarity, while the even-order term s are always positive. when the differential is taken, the even order terms cancel as shown in eq. 3. the third-order terms are not affected. one of the most common ways to drive a differen tial input adc is with a transformer. however, there are many applications wher e the adcs cannot be driven w ith transformers because the frequency response must extend to dc. in these cases, differential drivers are required. in cases where significant signal gain is required ahead of the adcs, differential amplifiers offer a good solution. although providing "noisele ss" voltage gain, transformers with turns ratios greater than two generally suffer from bandwidth and distorti on issues, especially at if frequencies. a block diagram of the ad813x and ada493x family of fully differential amplifiers optimized for adc driving is shown in figure 1. figure 1a s hows the details of the internal circuit, and figure 1b shows the equivalent circuit. th e gain is set by the external resistors r f and r g , and the common-mode voltage is set by the voltage on the v ocm pin. the internal common-mode feedback forces the v out+ and v out? outputs to be balanced, i.e., the signals at the two outputs are always equal in amplitude but 18 0 out of phase per the equation,
MT-075 v ocm = ( v out+ + v out? ) / 2. eq. 4 ~ r f r f r g r g v out? v out+ + ? gain = r f r g v in+ v in? (b) equivalent circuit: v ocm + ? + ? ? + + ? r f r f r g r g v in+ v in? v out+ v out? v ocm v+ v? (a) functional diagram v ocm v ocm r in, sem = r g 1 ? r f 2 (r f + r g ) r in, dm = 2 r g figure 1: ad813x, ad493x di fferential adc driver functional diagram and equivalent circuit the ad813x and ada493x uses two feedback loops to separately contro l the differential and common-mode output voltages. the differential fee dback, set with external resistors, controls only the differential output voltage. the comm on-mode feedback controls only the common- mode output voltage. this architecture makes it easy to arbitrarily set the output common-mode level in level shifting applications. it is force d, by internal common-mode feedback, to be equal to the voltage applied to the v ocm input, without affecting the differential output voltage. the result is nearly perfectly balanced differential outputs of identical amplitude and exactly 180 apart in phase over a wide frequenc y range. the circuit can be used wi th either a differential or a single-ended input, and th e voltage gain is equal to the ratio of r f to r g . the circuit can be analyzed using the assumptions and procedures summarized in figure 2. as in the case of op amp circuit dc analysis, one can first make the assumption that the currents into the inverting and non-inverting inpu t are zero (i.e., the input impeda nces are high relative to the values of the feedback resistors). the second assumption is that feedback forces the non- inverting and inverting input vol tages to be equal. the third assumption is that the output voltages are 180 out of phase and symmetrical about v ocm . page 2 of 9
MT-075 ~ r f r g r g v out? v out+ + ? gain = r f r g v in+ v in? v ocm r f i = 0 i = 0 v+ v? v+ = v? v ocm v ocm ? + and ? input currents are zero ? + and ? input voltages are equal ? output voltages are 180 out of phase and symmetrical about v ocm ? gain = r f /r g v out+ ?v out? v in+ ?v in? = figure 2: analyzing voltage level s in differential amplifiers even if the external feedback networks (r f /r g ) are mismatched, the internal common-mode feedback loop will still force the outputs to rema in balanced. the amplitudes of the signals at each output will remain equal and 180 out of ph ase. the input-to-output differential-mode gain will vary proportionately to the feedback mismatch, but the output balance will be unaffected. ratio matching errors in th e external resistors will result in a degradation of the circuit's ability to reject input common-mode signals, much the sa me as for a four-resistor difference amplifier made from a conventional op amp. also, if the dc levels of the input and out put common-mode voltages are different, matching errors will result in a small differential-mode output offset voltage. for the g = 1 case with a ground-referenced input signal and the output common-mode level set for 2.5 v, an output offset of as much as 25 mv (1% of th e difference in common-mode levels) can result if 1% tolerance resistors are used. resist ors of 1% tolerance will result in a worst case input cmr of about 40 db, worst case differential mode output offset of 25 mv due to 2.5 v level-shift, and no significant degradation in output balance error. the effective input impedance of a circu it, such as the one in figure 2, at v in+ and v in? will depend on whether the amplifier is being driven by a single-ended or differential signal source. for balanced differential input signals, the input impedance (r in,dm ) between the inputs ( v in+ and v in? ) is simply: r in,dm = 2 u r g eq. 5 page 3 of 9
MT-075 in the case of a single-ended i nput signal (for example, if v in? is grounded, and the input signal is applied to v in+ ), the input impedance becomes: () ? ? ? ? ? ? ? ? ? ? ? ? + ? = fg f g sem,in rr2 r 1 r r eq. 6 the circuit's single-ended input impedance is effectively higher than it would be for a conventional op amp connected as an inverter, because a fraction of the differential output voltage appears at the inputs as a common-m ode signal, partially bootstrapping the voltage across the input resistor r g . figure 3 shows some of the possible configurations for the ad813x differential amplifier. figure 3a is the standard co nfiguration which utilizes two fee dback networks, characterized by feedback factors 1 and 2, respectively. note that each fee dback factor can vary anywhere between 0 and 1. r g1 + r f1 + ? r f1 r g1 r f2 r g2 (a) 1 = g = 2 (1 ? 1) 1 + 2 r g1 r g2 + r f2 2 = r g2 + ? r f2 r g2 + ? r f1 r g1 (b) (d) v ocm v ocm + ? + ? r f1 r g1 (c) (e) v ocm v ocm 1 = 0 2 = 1 1 = 0 2 = 1 2 = 0 v ocm v+ v+ v+ v+ v+ v? v? v? v? v? v out? v out+ v out? v out+ v out? v out+ v out? v out+ v out? v out+ figure 3: some configurations for differential amplifiers figure 3b shows a configuration where there is no feedback from v out? to v+, i.e., 1 = 0. in this case, 2 determines the amount of v out+ that is fed back to v?, and the circuit is similar to a non-inverting op amp configuration, except for th e presence of the additional complementary output. therefore, the overal l gain is twice that of a non-inverting op amp, or 2 (1 + r f2 /r g2 ), or 2 (1/ 2). page 4 of 9
MT-075 figure 3c shows a circuit where 1 = 0 and 2 = 1. this circuit is essentially provides a resistorless gain of 2. figure 3d shows a circuit where 2 = 1, and 1 is determined by r f1 and r g1 . the gain of this circuit is always less than 2. finally, the circuit of figure 3e has 2 = 0, and is very similar to a conventional inverting op amp, except for the additional complementary output at v out+ . differential driver/receiver applications the ad813x/ada493x -series are also well suited to balanc ed differential line driving as shown in figure 4 where the ad8132 drives a 100- twisted pair cable. the ad8132 is configured as a gain of 2 driver to account for the factor of 2 lo ss due to the source and load terminated cable. in this configuration, the bandwidth of the ad8132 is approximately 160 mhz. + ? v in 49.9 499 1k 1k 523 49.9 49.9 v ocm ad8132 0.1f from 50 source +5v ?5v g m1 g m2 100 0.1f + + ? ? 0.1f 0.1f +5v ?5v 100 twisted pair ad8130 a = 1 v out ground 1 ground 2 v n + i 1 i 2 r2 r1 gain = 1 + r2 r1 figure 4: high speed diffe rential line driver, line receiver applications the line receiver is an ad8130 differential receiver which has a unique architecture called "active feedback" to achieve approximate ly 70 db common-mode rejection at 10 mhz. for a gain of 1, the ad8130 has a 3 db bandwidth of approximately 270 mhz. the ad8130 utilizes two identi cal input transconductance (g m ) stages whose output currents are summed together at a high impedance node and then buffered to the output. the output currents of the two g m stages must be equal but opposite in sign, therefore, the respective input voltages must also be equal but opposite in sign. the differential input si gnal is applied to one of the page 5 of 9
MT-075 stages (g m1 ), and negative feedback is applied to the other (g m2 ) as in a traditional op amp. the gain is equal to 1 + r2/r1. the g m1 stage therefore provides a tr uly balanced input for the terminated twisted pair for the best common-mode rejection. a number of triple drivers are available for dr iving rgb signals over ca t-5 cable such as the ad8133 , ad8134 , ad8146 , ad8147 , ad8148 . corresponding triple receivers are also available, including the ad8143 and ad8145 . the ad8123 (triple) and ad8128 (single) receivers also includ e adjustable line equalization. application example: ada4937-1 differential amplifier driving ad6645 14-bit 80/105msps adc the ad813x and ada493x family of differential drivers are su itable for use in dc or ac coupled applications with voltage gains of 1 to 4 (0 db to 12 db) and frequencies up to about 100 mhz (depending on the particul ar member of the family). they are especially useful as low distortion dc-coupled single-ended to diffe rential converters for driving differential input adcs. the v ocm feature can be used to level shift bipolar signals to match the common-mode input voltage of the adc. details of the circuit analysis of dc drivers and selection of resistor values is given in mt- xxx. the adisimdiffamp design tool, is also availabl e to facilitate these designs. the ada4937-1 is one of the latest in the series of differential amplifiers and is optimized for operation on a single +5 v supply. figure 5 shows it is used as a level shifter to drive the ad6645 14-bit 80/105 msps adc. (the ada4939-1 is a similar part optimized for voltage gains 2). 103 10 ?6 + ? ad6645 14-bit adc a in? a in+ v in +155mv 1.1v 61.5 200 207 207 228 24.9 24.9 +2.4v v ocm ada4937-1 0.1f 0.1f 0.1f +1.3v + / ? 0.275v +2.4v ? / + 0.55v +2.4v + / ? 0.55v 2.2v p-p differential input span +5v f s = 80/105msps v ref 5nv/ hz 1.57 270 10 6 = 103v rms ad6645 specs: input bw = 270mhz 1 lsb = 134v snr = 75db 5nv/ hz output noise = output snr = 20 log 0.778 = 77.6db +5v c ~ 50 2.2v figure 5: ada4937-1 drivi ng ad6645 in +5 v dc- coupled application page 6 of 9
MT-075 the circuit shown in figure 5 wi ll now be carefully analyzed in terms of signal swings and common-mode voltage levels. this is necessary to ensure all voltages fall within the allowable ranges specified by the devices. the ad6645 operates on a 2.2 v p-p differential si gnal with a common-mode voltage of +2.4 v. this means that each output of the ada4937 must swing between 1.85 v and 2.95 v which is within the output drive capability of the ada4937-1 operating on a single +5 v supply. the input signals must therefore swing be tween 1.025 v and 1.575 v which falls within the allowable input range of the ada4937-1 operating on a single +5 v supply. the input to the circuit is driven from a 50 source. the "bootstrapped" input impedance in the single-ended configurati on is approximately 267 . the 61.5 input termination resistor in parallel with the 267 gain setting resistor makes the overall impedance approximately 50 . note that a 228 resistor is inserted in series with th e inverting input. this is to match the net impedance seen by the noninverting input (200 + 61.5 ||50 = 200 + 28 = 228 ). without this extra 28 matching resistor in series with the original 200 gain setting resistor, the unbalanced source impedances cause an unwanted differential offset voltage to appear at the output. the increase in the bottom gain setting resistor from 200 to 228 requires that the feedback resistors be increased to 207 in order to maintain a gain of one. in practice, the nearest standard 1% resistors w ould be substituted for th e calculated values. the adisimdiffamp design tool is available to facilitate these designs and calculate the required resistor values for a specified gain and source impedance. the tool al so checks for violations of the input and output common-mode range limits of the differential amplifier. the output noise voltage spectral dens ity of the ada4937-1 is only 5 nv/ hz. this value includes the contributions of the feedback and gain resistors and is for g = 1. integrated over the input bandwidth of the ad6645 (270 mhz), this yi elds an output noise of 103 v rms. this corresponds to an snr of 77.6 db du e to the amplifier. note that the integration must be over the full input bandwidth of the adc since there is no external noise filter. the snr of the ad6645 is 75 db which corresponds to an input noise of 138 v rms. the combined noise due to the op amp (103 v) and the adc (138 v) is 172 v, yielding an overall snr of 73 db. if the full bandwidth of the ad6645 is not requir ed, a single-pole noise reduction filter can be added by selecting an appr opriate value for c. wideband ac coupled adc drive rs for if applications in the example shown in figure 6, we ar e digitizing a wideband signal with the ad9445 14-bit, 125 msps adc and desire to preserve as much of the adc input bandwidth as possible. therefore there is no interstage noise filter. page 7 of 9
MT-075 ad9445 14-bit 125msps adc +5v + ? v cm 0.1f 0.1f r g 0.1f ad8352 0.1f 160 g 10db z in = 2k || 3pf 24.9 24.9 r d 6.8k c d 0.2pf 0.1f 0.1f 24.9 24.9 macom etc-1-13 balun from 50 source output noise of ad8352 for 10db gain = 8.5nv/ hz integrated over 615mhz input bw of ad9445 = 264 v rms input referred noise of ad9445 = 158v rms total noise = 307 v rms snr = 67db for 2v p-p input 4.5mhz to 3ghz (buffered) ad9445 specs: 2v p-p fs diff. input bw = 615mhz 1 lsb = 122v snr = 73db ? ? ? ? ? figure 6: ad8352 2ghz differential amplifier driving ad9445 14-bit, 125msps adc the ad9445 has 615 mhz input bandwidth and an sfd r of 95 dbc for a 100 mhz input. for the driver, we have chosen the ad8352 2 ghz bandwidth differential amplifier because it has a resistor programmable gain range of 3 db to 21 db. the amplifier also has low noise (2.7 nv/ hz referred to the input for a gain setting of 10 db) and low distortion (82 dbc hd3 at 100 mhz). the lower end of the bandwidth re quirement is approximately 10 mhz. figure 6 shows the optimum ci rcuit configuration for driving the ad9445 with the 2 ghz ad8352 in a wideband application. the balun converts the single-e nded input to differential to drive the ad8352. although it is possible to c onfigure the ad8352 to accept a single-ended input (see ad8352 data sheet), optimum distor tion performance is obtained if it is driven differentially as shown. the c d /r d network is chosen to optimi ze the third-order intermodulation performance of the ad8352. the values are selected based on the desired gain and are given in the data sheet. the circuit yields an sfdr of 83 dbc for a 98.9 mhz input signal sampled at 105 msps. the output noise spectral density of the ad8352 for g = 10 is 8.5 nv/ hz. since there is no input filter, this must be in tegrated over the entire 615 mhz input bandwidth of the ad9445. snr of the combined amplifier and adc is 67 db. page 8 of 9
page 9 of 9 MT-075 references 1. hank zumbahlen, basic linear design , analog devices, 2006, isbn: 0-915550-28-1. also available as linear circuit design handbook , elsevier-newnes, 2008, isbn-10: 0750687037, isbn-13: 978- 0750687034. chapter 2. 2. walter g. jung, op amp applications , analog devices, 2002, isbn 0-916550-26-5, also available as op amp applications handbook , elsevier/newnes, 2005, isbn 0-7506-7844-5. chapter 3. 3. walt kester, analog-digital conversion , analog devices, 2004, isbn 0-916550-27-3, chapter 6. also available as the data conversion handbook , elsevier/newnes, 2005, isbn 0-7506-7841-0, chapter 6. 4. walt kester, high speed system applications , analog devices, 2006, isbn-10: 1-56619-909-3, isbn-13: 978-1-56619-909-4, chapter 2. 5. adisimdiffamp , an analog devices' on-line interactive design tool for differential amplifiers. copyright 2009, analog devices, inc. all rights reserved. analog devices assumes no responsibility for customer product design or the use or application of customers? products or for any infringements of patents or rights of others which may result from analog devices assistance. all trad emarks and logos are property of their respective holders. information furnished by analog devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by analog devices regarding technical accuracy and topicality of the content provided in analog devices tutorials.
|
